1. Technical Field
The present invention relates to a test apparatus and a test method. In particular, the present invention relates to a test apparatus and a test method for efficiently connecting and testing a plurality of devices under test.
2. Related Art
A semiconductor memory test apparatus connects a plurality of semiconductor memories, which are to be devices under test (DUT:device under test), and tests these semiconductor memories in parallel. Such a test apparatus includes pin resources, corresponding to terminals of the devices under test, and input and output a signal with respect to the terminals.
For example, a NOR-type flash memory includes an address input terminal, a control input terminal, a data input/output terminal, and a state output terminal. As an example, a NOR-type flash memory, which has a configuration of 16 M×16 bits, has 24 address input terminals, 7 control input terminals, 16 data input/output terminals, and one state output terminal. A conventional test apparatus includes a predetermined number of driver pin resources outputting a signal and a predetermined number of IO common pin resources inputting and outputting a signal, and assigns the driver pin resources to the address input terminals and to the control input terminals, and assigns the IO common pin resources to the data input/output terminals and to the state output terminal.
In addition, when testing a plurality of flash memories, when writing to a part of the flash memories has failed, it becomes necessary for a test apparatus to perform another writing to the flash memories to which writing has been failed, and to determine whether the writing was successful. Here, since there is a limitation in the number of writing to a flash memory, a test apparatus masks another writing to flash memories to which writing has succeeded, as is disclosed in Japanese Patent Application Publication No. 1995 (H3)-130200. In this way, when testing a plurality of devices under test, it is necessary for a test apparatus to enable control of the entire pin resources by classifying them for each device under test.
In view of this, in a conventional test apparatus, it becomes possible to assign the pin resources as a whole to each device under test, according to several kinds of predetermined division patterns. For example, when using 384 pin resources, the following division patterns have been selectable:    (1) Simultaneous Test of Four Devises Under Test
1st to 96th pin resources are assigned to a device under test 1, 97th to 192nd pin resources are assigned to a device under test 2, and 193rd to 288th pin resources are assigned to a device under test 3, and 289th to 384th pin resources are assigned to a device under test 4.    (2) Simultaneous Test of Eight Devices Under Test
1st to 48th pin resources are assigned to the device under test 1, and 49th to 96th pin resources are assigned to the device under test 2, . . . , and 337th to 384th pin resources are assigned to the device under test 8.    (3) Simultaneous Test of 16 Devices Under Test
1st to 24 pin resources are assigned to the device under test 1, and 25th to 48th pin resources are assigned to the device under test 2, . . . , and 361st to 384th pin resources are assigned to the device under test 16.
Recently, in response to the trend that the portable telephones, digital AV devices, IC cards, and so on are endowed with higher functions, semiconductor devices are becoming of higher integration. In addition, MCP (multi chip package) where a plurality of semiconductor memories and logics are installed in a single package is becoming common. Such a semiconductor device has a different number of terminals according to applications, and further has a different ratio between the number of input terminals to be connected to the driver pin resources and the number of input/output terminals to be connected to the IO common pin resources.
A general NAND-type flash memory receives an address using data input/output terminals. As one example, a NAND-type flash memory of 256M×16bits has 6 control input terminals, 16 data input/output terminals, and one state output terminal. Accordingly, when testing the NAND-type flash memory, the ratio between the required number of driver pin resources and IO common pin resources will be different from the corresponding ratio for a NOR-type flash memory.
A conventional test apparatus can only divide pin resources according to a predetermined division pattern, and that the number of the driver pin resources and the number of IO common pin resources included in each divided set of pin resources are also predetermined. Accordingly, depending on a device under test, there may be cases where pin resources cannot be assigned efficiently and many pin resources remain as redundant.
For example, when a device under test has 50 pins in the above example, 8 division that only assigns 48 pins for each device under test cannot be used, and 4 division is to be used. In this case, 96 pins are assigned for each device under test, and so 46 pins remain as redundant.
Moreover, for example when there is shortage in IO common pin resources included in a divided set of pin resources, it becomes necessary to reduce the number of devices under test that can be subjected to a simultaneous test even if the number of driver pin resource is sufficient.